top of page
+91-9019744344
Hands-on RTL Design
₹ 1500
1. Includes SystemVerilog for Design. 2. 25 handpicked questions to up your interview game. 3. Learn about skid buffers, fifos, valid-ready protocol and a lot more. 4. Designing complex microarchitectures with focus on PPA. 5. Converting microarchitecture details into real-world synthesizble RTL.
SystemVerilog for Design
₹ 1499
1. Various SystemVerilog language constructs useful for writing modern synthesisable RTL. 2. Understanding how sequential and combinatorial logic is converted into RTL. 3. Get exposed to converting microarchitecture to RTL. 4. Learn basic building-blocks like counters, shift-registers from ground up.
Online Courses: Courses
bottom of page